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BrianSune_Froum's avatar
BrianSune_Froum
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1 month ago

Cyclone 5 SoC FPGA Bank Supply Prerequisite

Dear Altera Support Team, I am not sure this is correct and did not found much info on Handbook. Device 5CSXF6C6U23 CASE 1: BANK 5A 5B only supplied VCCPD to 2.5V and VCCIO is floated. JTAG s...
Configuration
Generic Io
Power
Programmable Logic Device
BrianSune_Froum's avatar
BrianSune_Froum
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1 month ago

AqidAyman_Altera​ 

Then this is violating the HMC standard. When slot cards are not used the VCCIO could be floated and no supplied.

I cannot see the correlation between VCCIO and JTAG program fail.

VCCIO had nothing to do with JTAG scan unless JTAG is located in VCCIO 5A/5B.
VCCPGM or VCCIO BANK 3 is only the possible IO bank that can affected.

So which handbook or document have detail info on such.

Thanks,

Brian

AqidAyman_Altera's avatar
AqidAyman_Altera
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1 month ago

Hi Brian,

 

May I know what the error message you observed on the JTAG programs?

 

Regards,

Aqid

  • BrianSune_Froum's avatar
    BrianSune_Froum
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    1 month ago

    AqidAyman_Altera​ 

    I lost the data on that forgot to screen capture the board is testing on other side.
    I do recall the Quartus report wrong ID and always stuck on 93% final stage.

    The auto detect can sense both HPS and FPGA.

    All the tools are used to work properly on other C5 board and since the use of it.
    So the only factor is the board and the IO bank.

    When BANK 5A/B is forced to supply VCCIO there are no issue on JTAG programming.

    So please if there are any info that are not  welly documented please share.

    As BANK 5A/B do not have any relationship to JTAG or PGM bank as least from documents I studied.

    Thanks,

    Brian