May I know why you would like to use the Source synchronous mode?
Fyi, PLL compensation is not always needed. A PLL should be configured in direct (no compensation) mode unless a need for compensation is identified. Direct mode provides the best PLL jitter performance and avoids expending compensation clocking resources unnecessarily.
From the user guide link:
https://www.intel.com/content/www/us/en/docs/programmable/683771/current/i-o-pll-specifications.html#mcn1413265701682__fn_LimitedInQIIByIOMaxFreq_IOPLL
Although it states that the maximum frequency is 800 MHz for Input clock frequency:
Do note that *This specification is limited by the I/O maximum frequency. The maximum achievable I/O frequency is different for each I/O standard and is depends on design and system specific factors. Ensure proper timing closure in your design and perform HSPICE/IBIS simulations based on your specific design and system setup to determine the maximum achievable frequency in your system.
Additionally, could you check out this KDB article to see if it might be relevant to your case?https://www.intel.com/content/www/us/en/support/programmable/articles/000080391.html
Without a provided design, I may need some time to replicate the issue.
Regards,
Richard Tan
Contributor
