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lambert_yu's avatar
lambert_yu
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1 year ago
Solved

There's minimum pulse violation for IOPLL under source synchronous operation mode

Hi, I am facing one issue when I design the source synchronous lvds project. case: quartus II : 18.0.0 standard speed : 1.6Gbps; PLL : use external PLL ref clk for PLL: 800Mhz op...
Configuration
Generic Io
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Hi,


Do you able to share your project?


Regards,

Richard Tan


lambert_yu's avatar
lambert_yu
Icon for Contributor rankContributor
1 year ago

Hi, Richard

I coudn't export my design from internal network, and I only provide related configuration and related timing violation report, I don't know if it's okay for you to find the same issue. Related information as below figures:

And if I change the Compensation mode from synchrous -> direct, there's no this minimum pulse issue.

Best Regards,

Lambert