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lambert_yu's avatar
lambert_yu
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1 year ago
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There's minimum pulse violation for IOPLL under source synchronous operation mode

Hi, I am facing one issue when I design the source synchronous lvds project. case: quartus II : 18.0.0 standard speed : 1.6Gbps; PLL : use external PLL ref clk for PLL: 800Mhz op...
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sstrell's avatar
sstrell
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1 year ago

What is the target device?

When you say "external PLL", what do you mean? Are you using a PLL in the device or getting a clock from somewhere else? Either way, why is an 800 MHz clock being used as a reference clock? That seems unusual and I don't know if an FPGA PLL can handle that.

Your description of the setup is a bit unclear. Can you clarify exactly what you are doing and the setup?

lambert_yu's avatar
lambert_yu
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1 year ago

Hi, sstrell

I am sorry I made you confusion.

target device : arria 10 : 10ax115n2f45e1sg

For LVDS IP design, there's two PLL solution : external and internal; I used the external PLL solution. And just because it was usded in source synchronous design, and there's one following clock with data.The frequency of the following clock was 800Mhz (From arria 10 datasheet, the upper limit value is 800Mhz), and I made it as the reference clock for the IOPLL to generate fast clock, load clock and core clock which were used by lvds IP.

For IOPLL, I used the source synchronous operation mode, and met the above issue (minimum pulse violation for the fbclk_out enable ).

BRs,

Lambert