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lambert_yu's avatar
lambert_yu
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2 years ago
Solved

There's minimum pulse violation for IOPLL under source synchronous operation mode

Hi, I am facing one issue when I design the source synchronous lvds project. case: quartus II : 18.0.0 standard speed : 1.6Gbps; PLL : use external PLL ref clk for PLL: 800Mhz op...
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Generic Io
RichardT_altera's avatar
RichardT_altera
Icon for Super Contributor rankSuper Contributor
1 year ago

Thank you for acknowledging the solution provided. I'm pleased to know that your question has been addressed.


Now, I will transitioning this thread to community support. If you have any further questions or concerns, please don't hesitate to reach out. Please login to ‘https://supporttickets.intel.com’, view details of the desire request, and post a feed/response within the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support.

The community users will be able to help you on your follow-up questions.


Thank you and have a great day!


Best Regards,

Richard Tan