SDC problem

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i want to implement a SoC with the maximum frequency of my board StratixIV Gx.

I used one pll with two output, first output pll.c0=150Mhz, second output is 125Mhz. After a compilation and download the program to the board, and try to execute my C code, nothing that work.

When i use the same output clock, it work correctly.

How can i resolve this problem.

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You can only resolve it by understanding it.

'Nothing works' is too vague. If you said something like "Accesses to an Avalon-MM slave at address XXX from C code running on a NIOS II processor, causes the processor to lock-up (no communications) ..." that would be a little more specific.

If you have two clocks in the system, then I you must have clock-domain crossing logic in the system to ensure valid data transfers.

Have you tried simulating your design in Modelsim?

Cheers,

Dave

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You can only resolve it by understanding it.

'Nothing works' is too vague. If you said something like "Accesses to an Avalon-MM slave at address XXX from C code running on a NIOS II processor, causes the processor to lock-up (no communications) ..." that would be a little more specific.

If you have two clocks in the system, then I you must have clock-domain crossing logic in the system to ensure valid data transfers.

Have you tried simulating your design in Modelsim?

Cheers,

Dave

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Thank you for your reply

Sorry, since i don't explain the problem exactly. This the error message that appears on console

verifying 00040000 ( 0%)

verify failed between address 0x40000 and 0x4655f

leaving target processor paused

also it appear a window that contain problem occured downloading elf process failed.

I don't try to use a modelsim, because i don't know how can i use with nios-eclipse.

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This the error message that appears on console

verifying 00040000 ( 0%)

verify failed between address 0x40000 and 0x4655f

leaving target processor paused

also it appear a window that contain problem occured downloading elf process failed.

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So what is at that address? On-chip memory, external memory? Do you know that memory works correctly?

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I don't try to use a modelsim, because i don't know how can i use with nios-eclipse.

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If you are serious about doing FPGA development, then you need to learn to use all the tools. Modelsim is very useful for confirming that your system works, before you try to debug in hardware.

Cheers,

Dave

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So what is at that address? On-chip memory, external memory? Do you know that memory works correctly?

If you are serious about doing FPGA development, then you need to learn to use all the tools. Modelsim is very useful for confirming that your system works, before you try to debug in hardware.

Cheers,

Dave

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The address corresponds to on chip memory. I use just on-chip memory on my design.

For the memory worked correctly.

That range of addresses corresponds to 25952-bytes (25.24kB ).

Is there ~32kB of memory implemented at that address?

Cheers,

Dave

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That range of addresses corresponds to 25952-bytes (25.24kB ).

Is there ~32kB of memory implemented at that address?

Cheers,

Dave

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Yes there are 131,072Kb implemented at this adress. it start by 00040000 and finished by 0005ffff.

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Yes there are 131,072Kb implemented at this adress. it start by 00040000 and finished by 0005ffff.

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So what clock is used by the NIOS processor and to access that memory?

What does the TimeQuest timing report indicate for that data path, or for the clock domain used by the processor and memory?

Cheers,

Dave

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So what clock is used by the NIOS processor and to access that memory?

What does the TimeQuest timing report indicate for that data path, or for the clock domain used by the processor and memory?

Cheers,

Dave

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So what clock is used by the NIOS processor and to access that memory?

What does the TimeQuest timing report indicate for that data path, or for the clock domain used by the processor and memory?

Cheers,

Dave

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I use the same clock pll.c0=150Mhz,for the NIOs II and on-chip.

On TimeQuest timing i find some warning:

1-warning: timing characteristics of device ep4sgx230kf40c2 are preliminary.

2-warning: node: clk_inp was determined to be a clock but was found without an associated clock assignment.

3-warning: node: clk_0 was determined to be a clock but was found without an associated clock assignment.

4critical warning: timing requirements not met.

5-warning: clock uncertainty characteristics of the stratix iv device family are preliminary

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2-warning: node: clk_inp was determined to be a clock but was found without an associated clock assignment.

3-warning: node: clk_0 was determined to be a clock but was found without an associated clock assignment.

4critical warning: timing requirements not met.

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You need to constrain your clocks.

Read the documentation for TimeQuest. Download Rysc's document from the Altera Wiki and read that.

Cheers,

Dave

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You need to constrain your clocks.

Read the documentation for TimeQuest. Download Rysc's document from the Altera Wiki and read that.

Cheers,

Dave

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Think you very much for your help, i will read the documentation,:)