SDC problem

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If it closes timing at 250MHz, then from a static timing analysis perspective it will work. As for accelerating the design, there are many things but all design specific. I won't really be able to provide any guidance there.

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Ok thank you,

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I'm confused by the comment that Nios II works at 600MHz. I do not believe that is possible. Beyond that, generally the SOPC system(not just Nios) will limit the Fmax. Hooking up peripherals, etc. makes a large mux for data/address, which is slow.

475MHz is just over 2ns clock period. Once you start looking at paths in TimeQuest with report timing, you'll find that are generally longer than that. Stratix IV is the fastest FPGA fabric at 40nm(IMO), but what you're trying to do just doesn't seem to be close to possible.

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Thank you very much for your advice rysc, they let me win many time.

Just i need a small confirmation, my design it work with 250Mhz that mean that's fine?

If there are some technique that can accelerate my design will be welcome, car i need the helps from an expert as you rysc.

thank you very much :):)

I'm confused by the comment that Nios II works at 600MHz. I do not believe that is possible. Beyond that, generally the SOPC system(not just Nios) will limit the Fmax. Hooking up peripherals, etc. makes a large mux for data/address, which is slow.

475MHz is just over 2ns clock period. Once you start looking at paths in TimeQuest with report timing, you'll find that are generally longer than that. Stratix IV is the fastest FPGA fabric at 40nm(IMO), but what you're trying to do just doesn't seem to be close to possible.

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Aflatoun - You sent me an email through the forum, but your account has disabled receiving emails. You might want to change that, although to be honest, I prefer posting. Anyway, you stated the design is failing timing. You will need to launch TimeQuest from the GUI and then run Report All Summaries. There seem to be multiple failures, but Setup is probably the best place to start. Right-click on one of the failing domains and go to Report Timing. That allows you to get detailed path reports for analysis. I beleive the User Guide I posted has a discussion on report_timing, as that really is the bread and butter for analysis in TimeQuest.

Finally, you stated you were trying to run the design at 475MHz. I can pretty safely say that SOPC designs won't run that fast(very few designs run that fast). FPGA's are extremely powerful, and can often blow away processors in what they can do, but it's not achieved through high clock rates. Instead, pipelining and parallelism are the main work horses. Good luck.

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Hi Rysc,

First thank you very much for your reply, second i am so sorry about the disabled of receivings email, because i don't becareful about this option. Now it active. Yes i find many failures.

About the frequency rysc, i understand about you reply that isn't a good way to use 475Mhz because, may be this fast frequency can often blow away processors.

My problem, it is i have a code that run on 500 microsecond at 100Mhz, my application shoul be run at 0.5 micro-second. I bought Stratix IV Gx (EP4SGX230KF40C2) because i find that the NiosII on this board work with 600 Mhz. Please, can you clarify why 475Mhz frequency is too fast as you say,.

Second if i use the 250Mhz it is possible to reach the time that i need with some technique of optimisation, as uses LUT (i have log in my algorithm), implement same custom HDL as co-processor.

:(:(:(

Thank you .

Aflatoun - You sent me an email through the forum, but your account has disabled receiving emails. You might want to change that, although to be honest, I prefer posting. Anyway, you stated the design is failing timing. You will need to launch TimeQuest from the GUI and then run Report All Summaries. There seem to be multiple failures, but Setup is probably the best place to start. Right-click on one of the failing domains and go to Report Timing. That allows you to get detailed path reports for analysis. I beleive the User Guide I posted has a discussion on report_timing, as that really is the bread and butter for analysis in TimeQuest.

Finally, you stated you were trying to run the design at 475MHz. I can pretty safely say that SOPC designs won't run that fast(very few designs run that fast). FPGA's are extremely powerful, and can often blow away processors in what they can do, but it's not achieved through high clock rates. Instead, pipelining and parallelism are the main work horses. Good luck.

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You need to constrain your clocks.

Read the documentation for TimeQuest. Download Rysc's document from the Altera Wiki and read that.

Cheers,

Dave

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Think you very much for your help, i will read the documentation,:)

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2-warning: node: clk_inp was determined to be a clock but was found without an associated clock assignment.

3-warning: node: clk_0 was determined to be a clock but was found without an associated clock assignment.

4critical warning: timing requirements not met.

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You need to constrain your clocks.

Read the documentation for TimeQuest. Download Rysc's document from the Altera Wiki and read that.

Cheers,

Dave

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So what clock is used by the NIOS processor and to access that memory?

What does the TimeQuest timing report indicate for that data path, or for the clock domain used by the processor and memory?

Cheers,

Dave

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So what clock is used by the NIOS processor and to access that memory?

What does the TimeQuest timing report indicate for that data path, or for the clock domain used by the processor and memory?

Cheers,

Dave

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I use the same clock pll.c0=150Mhz,for the NIOs II and on-chip.

On TimeQuest timing i find some warning:

1-warning: timing characteristics of device ep4sgx230kf40c2 are preliminary.

2-warning: node: clk_inp was determined to be a clock but was found without an associated clock assignment.

3-warning: node: clk_0 was determined to be a clock but was found without an associated clock assignment.

4critical warning: timing requirements not met.

5-warning: clock uncertainty characteristics of the stratix iv device family are preliminary