Forum Discussion
Altera_Forum
Honored Contributor
15 years agoSDC problem
Hi, i want to implement a SoC with the maximum frequency of my board StratixIV Gx. I used one pll with two output, first output pll.c0=150Mhz, second output is 125Mhz. After a compilation and...
Altera_Forum
Honored Contributor
15 years agoAflatoun - You sent me an email through the forum, but your account has disabled receiving emails. You might want to change that, although to be honest, I prefer posting. Anyway, you stated the design is failing timing. You will need to launch TimeQuest from the GUI and then run Report All Summaries. There seem to be multiple failures, but Setup is probably the best place to start. Right-click on one of the failing domains and go to Report Timing. That allows you to get detailed path reports for analysis. I beleive the User Guide I posted has a discussion on report_timing, as that really is the bread and butter for analysis in TimeQuest.
Finally, you stated you were trying to run the design at 475MHz. I can pretty safely say that SOPC designs won't run that fast(very few designs run that fast). FPGA's are extremely powerful, and can often blow away processors in what they can do, but it's not achieved through high clock rates. Instead, pipelining and parallelism are the main work horses. Good luck.