Fail to enumerate RTile PCIe in the AVSTx8 configuration

Hi Divya,

The fact that your design works with AS x4 but not with Avalon-ST (AVST) x8 configuration points to a PCIe initialization/enumeration timing difference between the two configuration paths rather than an issue with the R-Tile PCIe IP itself. Here's what to check:

1. PCIe Reference Clock Availability

In CvP Initialization mode, the periphery image loads via AS x4 (Fast mode), and the core image loads via PCIe. The PCIe reference clock must be running for link training. Agilex™ 7 Configuration User Guide Even if you're not using CvP, the principle applies: ensure your PCIe reference clock is stable and running before the R-Tile begins link training, regardless of the FPGA configuration scheme used. AVST-based configuration timing can differ from AS x4, and if the PCIe refclk isn't ready in time, link training may fail silently.

2. Known CvP R-Tile Issue (if CvP is in your flow)

If your AVST x8 path involves a CvP update step, there is a documented issue to be aware of: In Quartus Prime Pro Edition software versions prior to 26.1, when using Agilex 7 R-Tile for Configuration via Protocol (CvP), the PCIe interface becomes non-functional after performing the CvP update, resulting in PCIe functional failures. Agilex® 7 M-Series Known Issue List During CvP update, the FPGA fabric is reconfigured and held in reset, while the PCIe hard IP is not reset. This reset issue occurs because the R-tile RTL is unable to handle the handshaking between hard IP and fabric after the CvP update. However, this issue does not cause the PCIe link to go down. Agilex® 7 M-Series Known Issue List The fix is to use Quartus Prime Pro 26.1 or later.

3. Enumeration Credit Handling

In some systems, there are broadcast Message TLPs being sent by the link partner during the PCIe enumeration process. Failing to properly initialize and return the corresponding credits from the Application logic to the R-Tile Avalon Streaming IP may cause enumeration issues due to the priority order between Message TLPs and the Completions required for Configuration TLPs. Application logic must ensure proper credits are returned to the R-Tile Avalon Streaming IP for any TLP that it receives. R-Tile Avalon® Streaming IP for PCI Express® User Guide This is a common root cause of "device not detected" symptoms even when the link is trained — it's worth verifying your application logic initializes and returns credits correctly before enumeration begins.

4. Use the R-Tile Debug Toolkit to Isolate the Failure

The R-Tile Debug Toolkit (DTK) is a System Console-based tool for R-Tile that provides real-time control, monitoring and debugging of the PCIe links. It allows you to monitor the IP configuration and link status, monitor the PCIe Configuration space, and monitor different counters for errors and event conditions. Overview

Specifically, check:

• Link Status: Indicates if the link (DL) is up or not. R-Tile Avalon® Streaming IP for PCI Express® User Guide
• Negotiated Speed: Indicates the negotiated speed during link training (2.5GT, 5.0GT, 8.0GT, 16.0GT, 32.0GT). R-Tile Avalon® Streaming IP for PCI Express® User Guide
• Negotiated Width: Indicates the negotiated link width during link training (x16, x8, x4, x2, x1). R-Tile Avalon® Streaming IP for PCI Express® User Guide

5. If You Are Using Configuration Mode 1 (2×8 PCIe)

Depending on the OPN being used, the R-Tile Avalon Streaming FPGA IP for PCIe allows the flexibility to handle the independent reset operation for each of the active PCIe cores when Configuration Mode 1 (2x8 Endpoint only) is selected. R-Tile Avalon® Streaming IP for PCI Express® User Guide Ensure your reset sequencing handles both cores correctly if you're operating in 2×8 mode.

Summary action items:

1. Confirm PCIe refclk is stable before FPGA user mode is entered in the AVST path.
2. If Quartus Prime Pro is older than 26.1 and CvP is involved, upgrade to 26.1+.
3. Verify application logic returns credits for all received TLPs before enumeration.
4. Use the R-Tile DTK via System Console to capture LTSSM state and link status at power-up under the AVST x8 configuration path.

If you can share the LTSSM state seen with the DTK when using AVST x8, that will significantly narrow down whether this is a link-training failure vs. an enumeration-level issue.

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Thank you very much.