Agilex 5 HPS EMIF - Differential Pair Polarity Inversion Support

For the Agilex 5 HPS DDR interface, is P/N swapping (polarity inversion) within a differential pair supported?

I could not find a clear statement in the Agilex 5 EMIF documentation.

Specifically:

1. Is polarity inversion supported for HPS DDR differential signals?
2. If yes, is any Quartus, HPS EMIF, or firmware configuration required?
3. If not, must polarity be preserved at the PCB level?
4. Is there a documentation section or application note that explicitly covers this requirement?

I am looking specifically for the Agilex 5 HPS EMIF/DDR interface, not a generic FPGA differential I/O or transceiver interface.