Agilex 5 HPS EMIF - Differential Pair Polarity Inversion Support

Hi sbj

Apologies for the delay in getting back. I searched through our database and the closest guide for your question is this EMIF IP user guide for Agilex 5 as the memory controller, the PHY, DQS clock trees and byte lane pin mapping are all shared hardware(both fabric and HPS) thus no special separate handling/documentation for just HPS EMIF alone (although there is additional constraints on certain scenarios like restriction and io bank usage)

https://docs.altera.com/r/docs/817467/26.1.1/external-memory-interfaces-emif-ip-user-guide-agilex-5-fpgas-and-socs/agilex-5-fpga-emif-ip-introduction

In the document

it states that both T/C (or P/N) polarity cannot be swapped in the documentation and as HPS shared the same hardware mem controller and IO96 byte lane structure as mentioned above , this requirement is also applicable to HPS EMIF. This also means polarity needs to be preserved at PCB levels

You can also refer to section 3.7 of the same documentation on the HPS EMIF portion for additional requirements

https://docs.altera.com/r/docs/817467/26.1.1/external-memory-interfaces-emif-ip-user-guide-agilex-5-fpgas-and-socs/agilex-5-emif-ip-for-hard-processor-subsystem-hps

Thanks

Regards

Kian