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Altera_Forum's avatar
Altera_Forum
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15 years ago

SDC problem

Hi, i want to implement a SoC with the maximum frequency of my board StratixIV Gx. I used one pll with two output, first output pll.c0=150Mhz, second output is 125Mhz. After a compilation and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

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I'm confused by the comment that Nios II works at 600MHz. I do not believe that is possible. Beyond that, generally the SOPC system(not just Nios) will limit the Fmax. Hooking up peripherals, etc. makes a large mux for data/address, which is slow.

475MHz is just over 2ns clock period. Once you start looking at paths in TimeQuest with report timing, you'll find that are generally longer than that. Stratix IV is the fastest FPGA fabric at 40nm(IMO), but what you're trying to do just doesn't seem to be close to possible.

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Thank you very much for your advice rysc, they let me win many time.

Just i need a small confirmation, my design it work with 250Mhz that mean that's fine?

If there are some technique that can accelerate my design will be welcome, car i need the helps from an expert as you rysc.

thank you very much :):)