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Honored Contributor
Honored ContributorSDC problem
Hi, i want to implement a SoC with the maximum frequency of my board StratixIV Gx. I used one pll with two output, first output pll.c0=150Mhz, second output is 125Mhz. After a compilation and...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- So what clock is used by the NIOS processor and to access that memory? What does the TimeQuest timing report indicate for that data path, or for the clock domain used by the processor and memory? Cheers, Dave --- Quote End --- --- Quote Start --- So what clock is used by the NIOS processor and to access that memory? What does the TimeQuest timing report indicate for that data path, or for the clock domain used by the processor and memory? Cheers, Dave --- Quote End --- I use the same clock pll.c0=150Mhz,for the NIOs II and on-chip. On TimeQuest timing i find some warning: 1-warning: timing characteristics of device ep4sgx230kf40c2 are preliminary. 2-warning: node: clk_inp was determined to be a clock but was found without an associated clock assignment. 3-warning: node: clk_0 was determined to be a clock but was found without an associated clock assignment. 4critical warning: timing requirements not met.
5-warning: clock uncertainty characteristics of the stratix iv device family are preliminary
