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Altera_Forum
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15 years ago

SDC problem

Hi, i want to implement a SoC with the maximum frequency of my board StratixIV Gx. I used one pll with two output, first output pll.c0=150Mhz, second output is 125Mhz. After a compilation and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

If it closes timing at 250MHz, then from a static timing analysis perspective it will work. As for accelerating the design, there are many things but all design specific. I won't really be able to provide any guidance there.