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Altera_Forum
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15 years ago

SDC problem

Hi, i want to implement a SoC with the maximum frequency of my board StratixIV Gx. I used one pll with two output, first output pll.c0=150Mhz, second output is 125Mhz. After a compilation and...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

--- Quote Start ---

2-warning: node: clk_inp was determined to be a clock but was found without an associated clock assignment.

3-warning: node: clk_0 was determined to be a clock but was found without an associated clock assignment.

4critical warning: timing requirements not met.

--- Quote End ---

You need to constrain your clocks.

Read the documentation for TimeQuest. Download Rysc's document from the Altera Wiki and read that.

Cheers,

Dave