Pin Planner LVDS Differential Pair Selection

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How do I make Pin Planner stop being so mean to me?

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You cannot. Its sole purpose in life is to frustrate you :)

For LVDS signals, you only need to assign the pin and IO_STANDARD to the positive side of the pair, and Quartus will infer the negative pin assignment. This means your top-level entity does not need to include your two signals, i.e., HSMC_RX_D_P and HSMC_RX_D_N, you can just call it HSMC_RX_D and make it LVDS. You then do not need an iobuf at the top-level of your design.

There are other solutions, but this one results in the least code :)

Cheers,

Dave

I think I am confused. At my top level I have:

input HSMC_CLKIN2, //Serial CLK IN_N

input [16:0] HSMC_RX_D

I then removed all assignments and re-imported my QSF that only contains the positive locations for HSMC_RX_D. Pin Planner automatically generates the _P and _N(n) locations. I removed the buffer from the top level. The only thing I'm trying to do is see the single ended signals. HSMC_RX_D[0] -> GPIO[0] -- there's no logic, no registers, no clocking. I had this working before by magic but I've since destroyed that code. But, I know the problem lies in the LVDS setting.

Also, the signals are not LVDS. When I set them to LVDS, (n)(n) appears, but it compiles w/o error. But still no signals on the GPIO.

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I think I am confused

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No problem, lets try to resolve that ... :)

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The only thing I'm trying to do is see the single ended signals.

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Hang on, you're changing your requirement here ...

Your interface has to either be defined as differential LVDS, in which case you cannot view the output signals unless you have a termination resistor across the output pair, or you want your signals as single-ended.

So what is your requirement?

Cheers,

Dave

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The signals are coming into the FPGA as differential and I have control over the ADC that is attached via the HSMC connector to enable 94 Ohm (and other values) resistors for termination.

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That does not make sense. If the ADC is sending LVDS signals to the FPGA, then the termination resistor is required at the end of the transmission line, i.e., at the FPGA.

Its possible that your ADC has the resistor option for another logic standard, eg., source terminations.

What is the part number of the ADC?

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So, I want to handle single ended signals within the FPGA, so they need to go through a buffer to become single ended, yes?

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No, you can define a receiver port as differential LVDS, and then only have the differential receiver output defined in your top-level entity, i.e., you can have a signal defined as my_lvds in your top-level entity and can consider that to be your differential receiver output and then in your pin assignments, the pin named my_lvds is the positive input and the pin named my_lvds(n) is the negative input. Yeah, its not exactly obvious ... and its a little confusing ...

Which FPGA board are you using? You need to make sure your FPGA supports differential LVDS termination, or that it has termination resistors on the board.

Cheers,

Dave

I'm replying from my phone.

First, thank you for your help. Second. I believe we are describing the same thing. I'm using TI's ADC 5282 EVM (evaluation module). I'm using the DE2-115 fpga oard.

The 8 channels, sync clock, and data clock are all differential. I think the voltage I/O is 1.5 V. I selected LVDS because it didn't specify a voltage level and I didn't want to deal with conflicting voltage standard between different I/O banks. The GPIO and HSMC are supposedly on unique banks to all other components but I still received I/O standard errors. The ADC can run at 65 MSPS, however, we probably won't go above 5-10.

So, the channel 0 comes over to RX D P[4] and RX D N[4]. To manage the signal inside of the FPGA, I first run it through an IO buffer to make it single ended, yes?

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First, thank you for your help

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You're welcome. FPGAs can be pretty confusing to start with :)

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I'm using TI's ADC 5282 EVM (evaluation module)

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Ok. According to the main page ...

http://www.ti.com/tool/ads5282evm

the output signals are LVDS.

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I'm using the DE2-115 fpga board

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Ok. To receive LVDS on this board you have to do two things;

1. Set the VCCIO jumper to 2.5V to allow LVDS constraint on the HSMC pins.

See the DE2-115 schematic, p23, the LVDS signals input to Bank 5 and 6, and see p27 for the power jumper settings, jumper JP7 pin 5+6 to select VCCIO = 2.5V for banks 5+6.

2. Manually solder the 100-ohm terminations onto the board.

See the DE2-115 schematic, p23 where the termination resistors are marked DNI = do not install. Meaning that you have to install them :)

Have you done both of these steps?

Then you also need to create a spreadsheet with the HSMC pin assignments on your evaluation board and what it connects to on the DE2-115 to make sure all signals are compatible.

Cheers,

Dave

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1. Set the VCCIO jumper to 2.5V to allow LVDS constraint on the HSMC pins.

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I was reading the tutorial that came along with the software; I thought the input signals should be 1.5V (both digital and analog), so I set everything to 1.5V. Only the analog signals are 1.5V. I have changed the jumpers to 2.5V again.

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2. Manually solder the 100-ohm terminations onto the board.

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I am fearful of soldering anything to the FPGA because it may be used for many other projects. My pin planner looks like garbage. I think there are 3 levels of (n)s. However, the darn thing works. I tested the speeds up to 50 MHz in (300 MHz out) and without using termination, the signals appear to arrive at the FPGA correctly. After the code is complete I will do extensive testing, and if we require 100 Ohm resistors, we will (painfully) attach them.

Again, thank you for your help. I don't know how it's working, like I said pin planner looks like garbage. But it is. Moving on. Not touching it.

-Joe

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I am fearful of soldering anything to the FPGA because it may be used for many other projects.

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Where are the resistors? On the BGA pads, or away from the FPGA? If they are away from the FPGA, then you should not be scared to solder :)

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My pin planner looks like garbage. I think there are 3 levels of (n)s.

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The pin planner does not technically need any (n)s. If you define the positive side as LVDS, then the negative side is inferred. You can always copy the project to a new folder, and then delete constraints until you either break something, or clean it up.

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However, the darn thing works. I tested the speeds up to 50 MHz in (300 MHz out) and without using termination, the signals appear to arrive at the FPGA correctly. After the code is complete I will do extensive testing, and if we require 100 Ohm resistors, we will (painfully) attach them.

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Look at the signals at the FPGA with an oscilloscope and the signals probably look nasty :)

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Again, thank you for your help. I don't know how it's working, like I said pin planner looks like garbage. But it is. Moving on. Not touching it.

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That is fine. However, if you start calculating the performance of your ADC, eg., INL and DNL, then you may be getting bit errors over the LVDS links that make things look worse.

The bottom line is, do not be afraid of soldering. If you've never done it before, then go find a dead PC, pull out a PCI board, and start removing parts from that and then soldering them back on again. Once you feel comfortable doing that, you can add the terminations onto the DE115 board :)

Cheers,

Dave

I'm not afraid of actually soldering, it's just they're super tiny components. And I don't want to solder them only to have to remove them because the FPGA board is used for something else.

I'm sure the signals look nasty at 300 Mhz. However, we probably won't go above 10 Mhz (60 MHz out).

The Pin Planner tool keeps locking me out from making changes after I select LVDS. Either it will prevent me from changing something (ignore my change) or prevent me from deleting something.