Pin Planner LVDS Differential Pair Selection

I'm replying from my phone.

First, thank you for your help. Second. I believe we are describing the same thing. I'm using TI's ADC 5282 EVM (evaluation module). I'm using the DE2-115 fpga oard.

The 8 channels, sync clock, and data clock are all differential. I think the voltage I/O is 1.5 V. I selected LVDS because it didn't specify a voltage level and I didn't want to deal with conflicting voltage standard between different I/O banks. The GPIO and HSMC are supposedly on unique banks to all other components but I still received I/O standard errors. The ADC can run at 65 MSPS, however, we probably won't go above 5-10.

So, the channel 0 comes over to RX D P[4] and RX D N[4]. To manage the signal inside of the FPGA, I first run it through an IO buffer to make it single ended, yes?