--- Quote Start ---
The signals are coming into the FPGA as differential and I have control over the ADC that is attached via the HSMC connector to enable 94 Ohm (and other values) resistors for termination.
--- Quote End ---
That does not make sense. If the ADC is sending LVDS signals to the FPGA, then the termination resistor is required at the end of the transmission line, i.e., at the FPGA.
Its possible that your ADC has the resistor option for another logic standard, eg., source terminations.
What is the part number of the ADC?
--- Quote Start ---
So, I want to handle single ended signals within the FPGA, so they need to go through a buffer to become single ended, yes?
--- Quote End ---
No, you can define a receiver port as differential LVDS, and then only have the differential receiver output defined in your top-level entity, i.e., you can have a signal defined as my_lvds in your top-level entity and can consider that to be your differential receiver output and then in your pin assignments, the pin named my_lvds is the positive input and the pin named my_lvds(n) is the negative input. Yeah, its not exactly obvious ... and its a little confusing ...
Which FPGA board are you using? You need to make sure your FPGA supports differential LVDS termination, or that it has termination resistors on the board.
Cheers,
Dave
Honored Contributor
