Forum Discussion
Altera_Forum
Honored Contributor
11 years agoI think I am confused. At my top level I have:
input HSMC_CLKIN2, //Serial CLK IN_N input [16:0] HSMC_RX_D I then removed all assignments and re-imported my QSF that only contains the positive locations for HSMC_RX_D. Pin Planner automatically generates the _P and _N(n) locations. I removed the buffer from the top level. The only thing I'm trying to do is see the single ended signals. HSMC_RX_D[0] -> GPIO[0] -- there's no logic, no registers, no clocking. I had this working before by magic but I've since destroyed that code. But, I know the problem lies in the LVDS setting. Also, the signals are not LVDS. When I set them to LVDS, (n)(n) appears, but it compiles w/o error. But still no signals on the GPIO.