Locked signal stays low for Cyclone V PLL

It is my presumption that locked should go, and stay high.

The source is a 50MHz clock module and this has already been used to create a fractional PLL working at 148.5MHz for an HDMI clock and the evidence shows this is stable. This was another design to prove the HDMI interface.

I am using signal tap and looking directly at the locked signal. It stays low.

Many thanks for your reply.

Many thanks for your offer.

I have uploaded a cut-down version of my design to include just the PLL and signal tap in a zip file . I hope this has all the information you need.

The clock for signal tap is the 300MHz generated clock. This is then divided by 6 so a direct comparison of timing can be made with the reference clock. I believe the reference and 300MHz clocks are both stable and consistent with each other.

I might have expected the Locked signal to go in and out of lock if there were any stability issues.

Hopefully it will be obvious that I'm doing something wrong.

I've pulled out the local rst signal for the PLL IP and added that to signal tap.

I can confirm the locked signal never goes high. If I try and trigger a signal tap capture with this signal transition going high it never happens.

This is quite a simple project to test the failure. I'm surprised I seem alone in having this issue.

Many thanks for trying this out.

The crystal module is a EC3645TS-50.000M TR

The datasheet: https://abracon.com/datasheets/Ecliptek/EC36.pdf

It should have low jitter and low sensitivity to ripple on it's power rail.

I've checked with a 1GS/s scope and jitter after 10uS is consistent with +/-1ns sampling scope capabilities. It is confirmed by a scope to be nominal 50MHz.

Both the 2.5V for the PLL supply and 3.3V rails have ~40mv p-p ripple that should be within spec. The same +3.3V is supplied to the crystal and the FPGA VCCIO associated with the input so any ripple should track thresholds.

There are two clock pins attached to the FPGA, I have tried both as the reference clock in the PLL and locked remains low. I have tried 3.3V-TTL and 3.3V-LVCMOS pin input thresholds.

I've tried different settings such as low bandwidth.

For now I have put this issue on hold as the 300MHz clock seems stable for my needs.

Can there be any other cause I haven't considered?

Sorry it's taken so long to reply.

The Locked signal would stay high if I set the "PLL Bandwidth Preset" to "High".

I also added some extra decoupling on the 2.5V rail.

I also entered the clock period into the Timing Analyser as I wasn't sure if the dips in the lock signal were due to SignalTap sampling.

It's now reliably high.