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Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
3 years ago

Locked signal stays low for Cyclone V PLL

I'm using a simple PLL using a 50MHz clock source to produce a 300MHz clock using a PLL IP in simple "Integer-N PLL" mode. The 300MHz clock is fine and if I divide by 6 and count I can compare it ...
Ash_R_Altera's avatar
Ash_R_Altera
Icon for Regular Contributor rankRegular Contributor
3 years ago

Hi,

As there is no further response to the case, I am setting the case to closure. However, it will still be open for the community members to comment. Please feel free to open a new case if you need support.


Regards



  • Mikexx's avatar
    Mikexx
    Icon for Occasional Contributor rankOccasional Contributor
    3 years ago

    Sorry it's taken so long to reply.

    The Locked signal would stay high if I set the "PLL Bandwidth Preset" to "High".

    I also added some extra decoupling on the 2.5V rail.

    I also entered the clock period into the Timing Analyser as I wasn't sure if the dips in the lock signal were due to SignalTap sampling.

    It's now reliably high.

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