MAX10 FPGA IOs not entering Tri-state (Hi-Z)

Question

Hello Team,I am using 10M16 FPGA and observed that the IOs are not getting tri-stated/ Hi-Z state after:The Reset is released through a switch / press button on "DEV_CLRN" pin, considering there is no .sof/ .pof code flashed.Hardware Configuration:&nbsp;"DEV_OE" pin is Grounded with 10K resistor.Reference: Intel® MAX® 10 Device Handbook - Combined&nbsp;Pin NamePin FunctionsPin DescriptionConnection Guidelines&nbsp;DEV_OEInput, I/O&nbsp;This is a dual-purpose pin. Optional pin that allows you tooverride all tristates on the device.When this pin is driven low, all I/O pins are tristated. Whenthis pin is driven high, all I/O pins behave as programmed.You can enable this pin by turning on the Enable devicewide output enable (DEV_OE) option in the Quartus Primesoftware.Altera recommends you to tie the DEV_OE pin to GND whenthe Enable device-wide output enable (DEV_OE) optionis disabled and not used as a user I/O pin. You can also tiethe DEV_OE pin to VCCIO or leave the DEV_OE pinunconnected provided that the Enable device-wide outputenable (DEV_OE) option is disabled and not used as a userI/O pin. When you leave the DEV_OE pin unconnected, Alterarecommends you to set the DEV_OE pin to input tristate witha weak pull-up.

fvm · Answer

Hi Patrick,I believe this is a misunderstanding. DEV_OE pin is only functional in user mode (with valid configuration loaded) when enabled in device and&nbsp; pin options. Default IO pin state is three-state with weak pull-up, that's what you'll see before loading .sof or configuration from non-volatile memory.RegardsFrank&nbsp;

aqidayman_altera · Answer

Hi,
&nbsp;
Please refer to the link below on the I/O pins' behaviour during every configuration sequence:
https://docs.altera.com/r/docs/683865/current/max-10-fpga-configuration-user-guide/configuration-sequence
&nbsp;
Regards,Aqid

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MAX10 FPGA IOs not entering Tri-state (Hi-Z)

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Pin Name	Pin Functions	Pin Description	Connection Guidelines
DEV_OE	Input, I/O	This is a dual-purpose pin. Optional pin that allows you to override all tristates on the device. When this pin is driven low, all I/O pins are tristated. When this pin is driven high, all I/O pins behave as programmed. You can enable this pin by turning on the Enable device wide output enable (DEV_OE) option in the Quartus Prime software.	Altera recommends you to tie the DEV_OE pin to GND when the Enable device-wide output enable (DEV_OE) option is disabled and not used as a user I/O pin. You can also tie the DEV_OE pin to VCCIO or leave the DEV_OE pin unconnected provided that the Enable device-wide output enable (DEV_OE) option is disabled and not used as a user I/O pin. When you leave the DEV_OE pin unconnected, Altera recommends you to set the DEV_OE pin to input tristate with a weak pull-up.