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patrick03's avatar
patrick03
Icon for New Contributor rankNew Contributor
3 months ago

MAX10 FPGA IOs not entering Tri-state (Hi-Z)

Hello Team, I am using 10M16 FPGA and observed that the IOs are not getting tri-stated/ Hi-Z state after: The Reset is released through a switch / press button on "DEV_CLRN" pin, considering there...
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FvM's avatar
FvM
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3 months ago

Hi Patrick,

I believe this is a misunderstanding. DEV_OE pin is only functional in user mode (with valid configuration loaded) when enabled in device and  pin options. Default IO pin state is three-state with weak pull-up, that's what you'll see before loading .sof or configuration from non-volatile memory.

Regards
Frank