Forum Discussion
Mikexx
Occasional Contributor
Occasional ContributorLocked signal stays low for Cyclone V PLL
I'm using a simple PLL using a 50MHz clock source to produce a 300MHz clock using a PLL IP in simple "Integer-N PLL" mode.
The 300MHz clock is fine and if I divide by 6 and count I can compare it ...
FvM
Super Contributor
Super ContributorHello,
can you show all parameters that are defining the PLL? What's the input clock source?
Regars,
Frank
can you show all parameters that are defining the PLL? What's the input clock source?
Regars,
Frank
