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Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Locked signal stays low for Cyclone V PLL

I'm using a simple PLL using a 50MHz clock source to produce a 300MHz clock using a PLL IP in simple "Integer-N PLL" mode. The 300MHz clock is fine and if I divide by 6 and count I can compare it ...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,

Can you bring the 'global_reset' as well in your signal tap?

PLL may need some more time to get properly locked to the clock. Once it is out of reset, it may start giving the output clock, but it still may not be the correct one.

Consider the PLL output clock valid only when the locked signal is asserted.

Recommend you to run the signal tap for some more time and trigger on the locked signal.

​

Regards


Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

I've pulled out the local rst signal for the PLL IP and added that to signal tap.

I can confirm the locked signal never goes high. If I try and trigger a signal tap capture with this signal transition going high it never happens.

This is quite a simple project to test the failure. I'm surprised I seem alone in having this issue.