Locked signal stays low for Cyclone V PLL

Many thanks for your offer.

I have uploaded a cut-down version of my design to include just the PLL and signal tap in a zip file . I hope this has all the information you need.

The clock for signal tap is the 300MHz generated clock. This is then divided by 6 so a direct comparison of timing can be made with the reference clock. I believe the reference and 300MHz clocks are both stable and consistent with each other.

I might have expected the Locked signal to go in and out of lock if there were any stability issues.

Hopefully it will be obvious that I'm doing something wrong.