JESD204B RX Link Never Achieves CGS at 12.8 Gbps on S10 ES (1SG280LU3F50E3VGS1, Quartus Pro 17.1)

Hi Team,

I am using the Intel JESD204B RX Example Design on a Stratix 10 GX Engineering Sample FPGA (1SG280LU3F50E3VGS1, L-Tile) with Quartus Prime Pro 17.1.I have two JESD204B configurations using the same board, RTL, and hardware.

Case 1 (Working):ADC Clock = 1228.8 MHz,

Decimation = 6

Lane Rate = 8.192 Gbps

REFCLK (Core/XCVR) = 409.6 MHz

Link/Frame Clock = 204.8 MHz

SYSREF = 6.4 MHz

This configuration works correctly and the JESD link comes up successfully.

Case 2 (Not Working):

ADC Clock = 1280 MHz

Decimation = 4

Lane Rate = 12.8 Gbps

REFCLK (Core/XCVR) = 640 MHz

Link/Frame Clock = 320 MHz

SYSREF = 5 MHz

The JESD204B parameters are identical in both cases:

L = 4 M = 8 F = 4 S = 1 N = 16 NP = 16 K = 32 Subclass 1

In the failing case, the following status is observed:

Core PLL Locked = Yes

ADC PLL Locked (Register 0x056F = 0x80)

rx_is_lockedtodata = 0xF

rx_ready = 0x0F

rx_cal_busy = 0

rx_analogreset = 0

rx_digitalreset = 0

jesd204_rx_link_ready = 1

jesd204_rx_link_valid = 0

The Debug Link Buffer outputs are always zero:

jesd204_rx_dlb_kchar_data = 0

jesd204_rx_dlb_data_valid = 0

jesd204_rx_dlb_data = 0

jesd204_rx_dlb_disperr = 0

jesd204_rx_dlb_errdetect = 0

Therefore, no CGS (/K28.5/) characters are detected and the link never progresses beyond this point.

I have verified the following:

ADC SPI configuration is correct.SYSREF is present on both ADC and FPGA.Register 0x0120 is written with 0x1C and correctly reads back 0x18 after SYSREF capture.Register 0x056E is configured correctly for the 12.8 Gbps lane rate.Register 0x0201 is set correctly for decimation by 4.REFCLK, Link Clock, and Frame Clock frequencies are correct.Native PHY calibration completes successfully.No Quartus warnings are reported.The Intel example design is used without RTL modifications.I also tried lane swapping and RX polarity inversion, but the result was unchanged.This 12.8 Gbps configuration has never worked even once since the beginning, whereas the 8.192 Gbps configuration works reliably on the same hardware.

Could you please advise: Is there any known limitation or errata for Stratix 10 ES (1SG280LU3F50E3VGS1 L-Tile) at 12.8 Gbps?Is any additional Native PHY or transceiver configuration required for 640 MHz reference clock and 12.8 Gbps lane rate?Are there any known issues in Quartus Prime Pro 17.1 related to JESD204B RX at this operating point?Any suggestions on additional debug steps would be greatly appreciated.