MAX 10: Can an ASx1 RBF be written directly to internal CFM via on-chip flash Avalon-MM?

Hi,

I am implementing an in-system self-update mechanism for an Intel MAX 10 FPGA (10M16SAU169I7G) and I would like to confirm the correct configuration image format for programming the internal CFM through logic running inside the FPGA.

My setup

• Device: MAX 10 10M16SAU169I7G
• Current design already boots normally from internal flash
• Inside the running design, I receive a new FPGA image over UART
• I split the image into blocks, verify CRC, and then write the data into the internal CFM using the on-chip flash IP Avalon-MM data interface
• After the transfer is complete, I plan to power-cycle the board so the FPGA boots from the newly written image

What I am currently doing

I generate the update file using quartus_cpf from the .sof:

~.bat
'''
quartus_cpf ^
--option=bitstream_compression=off ^
--configuration_mode=ASx1 ^
-c ^
input.sof ^
output_file_active_serial.rbf
'''

Then I send this .rbf file to the FPGA and write it word-by-word into the internal CFM.

My question

Can a Raw Binary File (.rbf) generated from a MAX 10 .sof with --configuration_mode=ASx1 be written directly into the MAX 10 internal CFM through the on-chip flash Avalon-MM interface, and then be used successfully as a bootable configuration image after power cycle?

Or, stated differently:

• Is the ASx1 RBF byte layout identical to the internal CFM configuration image layout expected by MAX 10?
• If not, what is the correct file format / conversion flow for self-updating the internal CFM from user logic?
• Should I be using RBF, POF, or another file/image format for this purpose?
• Is there any official Intel example or application note showing the correct way to write a new configuration image into MAX 10 CFM from inside the running FPGA design?

Additional context

I already reviewed:

• MAX 10 FPGA Configuration User Guide
• Remote System Upgrade in Intel MAX 10 Devices
• Using the MAX 10 User Flash Memory

From the documentation, I understand that MAX 10 supports configuration from JTAG and internal flash, and that remote/dual configuration is supported. However, I could not find a clear statement confirming whether an ASx1-generated RBF is the correct binary image to write directly into CFM via Avalon-MM.

My main concern is avoiding a situation where:

• the UART transfer is correct,
• the CFM write completes,
• but the FPGA does not boot afterwards because the file format/layout written into CFM is not the expected one.

If anyone from Intel or anyone who has implemented MAX 10 self-update / remote update can clarify the correct image format and recommended flow, I would appreciate it.

Thank you.