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Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

Locked signal stays low for Cyclone V PLL

I'm using a simple PLL using a 50MHz clock source to produce a 300MHz clock using a PLL IP in simple "Integer-N PLL" mode. The 300MHz clock is fine and if I divide by 6 and count I can compare it ...
Ash_R_Intel's avatar
Ash_R_Intel
Icon for Regular Contributor rankRegular Contributor
2 years ago

Hi,

You are right. "Locked" signal should stay high.

But, in spite of locked = '0' are you seeing a stable clock output? This sounds strange.

Can you check if you are probing the right PLLs locked output in signal tap?


Regards


Mikexx's avatar
Mikexx
Icon for Occasional Contributor rankOccasional Contributor
2 years ago

It is my presumption that locked should go, and stay high.

The source is a 50MHz clock module and this has already been used to create a fractional PLL working at 148.5MHz for an HDMI clock and the evidence shows this is stable. This was another design to prove the HDMI interface.

I am using signal tap and looking directly at the locked signal. It stays low.

Many thanks for your reply.