Forum Discussion
Mikexx
Occasional Contributor
Occasional ContributorLocked signal stays low for Cyclone V PLL
I'm using a simple PLL using a 50MHz clock source to produce a 300MHz clock using a PLL IP in simple "Integer-N PLL" mode.
The 300MHz clock is fine and if I divide by 6 and count I can compare it ...
Ash_R_Altera
Regular Contributor
Regular ContributorCan you please share your design with us to reproduce the issue at our end?
Regards
MikexxMany thanks for your offer.
I have uploaded a cut-down version of my design to include just the PLL and signal tap in a zip file . I hope this has all the information you need.
The clock for signal tap is the 300MHz generated clock. This is then divided by 6 so a direct comparison of timing can be made with the reference clock. I believe the reference and 300MHz clocks are both stable and consistent with each other.
I might have expected the Locked signal to go in and out of lock if there were any stability issues.
Hopefully it will be obvious that I'm doing something wrong.
