Occasional Contributor
Regular ContributorHi,
I tried your design on a Cyclone V SoC dev kit with corresponding pin changes. It works fine for me. See the screen shot.
Please check if you are providing a stable 50MHz clock to the PLL.
Regards
Occasional ContributorMany thanks for trying this out.
The crystal module is a EC3645TS-50.000M TR
The datasheet: https://abracon.com/datasheets/Ecliptek/EC36.pdf
It should have low jitter and low sensitivity to ripple on it's power rail.
I've checked with a 1GS/s scope and jitter after 10uS is consistent with +/-1ns sampling scope capabilities. It is confirmed by a scope to be nominal 50MHz.
Both the 2.5V for the PLL supply and 3.3V rails have ~40mv p-p ripple that should be within spec. The same +3.3V is supplied to the crystal and the FPGA VCCIO associated with the input so any ripple should track thresholds.
There are two clock pins attached to the FPGA, I have tried both as the reference clock in the PLL and locked remains low. I have tried 3.3V-TTL and 3.3V-LVCMOS pin input thresholds.
I've tried different settings such as low bandwidth.
For now I have put this issue on hold as the 300MHz clock seems stable for my needs.
Can there be any other cause I haven't considered?
