delay in verilog

you want to insert one "clock" delay?(I don't think so)

or delay for some nsec(or psec)?

you can not create delay in HDL unless you put delayed clock with main clock.

don't you have extra PLL out pins?

Before we have to guess further about PLL usage, you should tell about the original problem as clear as possible.

Consider learning FPGA design step by step. You don't need to take all at once.

Right.

What do you really want?

I mean why you want a delay in your design?

I will answer you as much as I can.

ok, this is my code. Right now, it SEEMS to work. If anyone would take a look and send me feedback, I would appreciate a lot.

--- Quote Start ---

module delay_finite_state (

clock,

reset,

ready,

dout_ready,

din_data,din_valid,din_sop,din_eop,

dout_data,dout_valid,dout_sop,dout_eop

);

input clock;

input reset;

input ready;

input [15:0]din_data;

input din_valid,din_sop,din_eop;

output reg [15:0] dout_data;

output reg dout_valid,dout_sop,dout_eop;

output dout_ready;

reg [1:0] fstate;

reg [1:0] reg_fstate;

reg [19:0] reg1,reg2,reg3,reg4,reg5,reg6,reg7,reg8,reg9,reg10,

reg11,reg12,reg13,reg14,reg15;

parameter idle=0,run=1;

always @(posedge clock)

begin

fstate <= reg_fstate;

end

always @(fstate or reset or ready)

begin

if (reset) begin

reg_fstate <= idle;

end

else begin

case (fstate)

idle: begin

if (ready) reg_fstate <= run;

// Inserting 'else' block to prevent latch inference

else

reg_fstate <= idle;

end

run: begin

reg1<={din_data, din_valid, din_sop, din_eop};

reg2<=reg1;

reg3<=reg2;

reg4<=reg3;

reg5<=reg4;

reg6<=reg5;

reg7<=reg6;

reg8<=reg7;

reg9<=reg8;

reg10<=reg9;

reg11<=reg10;

reg12<=reg11;

reg13<=reg12;

reg14<=reg13;

reg15<=reg14;

{dout_data,dout_valid,dout_sop,dout_eop}<=reg15;

if (~(ready)) reg_fstate <= idle;

// Inserting 'else' block to prevent latch inference

else reg_fstate <= run;

end

default: begin

$display ("Reach undefined state");

end

endcase

end

end

assign dout_ready=ready;

endmodule // SM1

--- Quote End ---

thanks for your reply.

Well, I am trying to make a video elaboration system with to branches. One branch should perform a lowpass effect on the video (a 2d fir, or a 2d median qith custom logic, not altera's ones) and the other branch should propagate video packets without elaborations. The custom block has a latency of (~)12 clock cycles, and I need the two branches to be aligned.

So, I was thinking to add a delay on the branch without elaboration, but it seems I am somhow wrong.

I did other kind of delay bloks for my system without using fsm, but they do not work too good..

Thanks for your hint.

Anyway, I've tried but sop and eop signals seems to work fine.

The valid signal, I don't know. I'll take a picture of the image on the monitor becouse is quite difficult to explain the effect I am seeing..

Now I'll try to delay ONLY active data/sop/eop signals ( according to the valid signal) ant to (re)generate a valid signal as output locked to the data/sop/eop.