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Altera_Forum's avatar
Altera_Forum
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15 years ago

delay in verilog

How can I insert one delay in a program but not in a simulation in verilog!?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
15 years ago

Right.

What do you really want?

I mean why you want a delay in your design?

I will answer you as much as I can.