Help on understanding Agilex5 speed binning and static power

Agilex 5 parts have  high static power by industry  traditions, so using Agilex in our designs needs some attention. 

Using the PTA  26.1.110: fixed junction temperature

Is there going to be facility in the PTA to vary the core power supply values over the min and max range ? via tcl ?
Will there be a model update soon? most of the values I get seem same for ES and production silicon in the PTA.

(static power , 50 deg C, typical )  power of 100 DSPs at 200 MHz, + LPDDR4(32 + usage defaults)

A5EE008BB23BE6X   : 551mW ,   + 200mW, +576 mW
A5EE008BB23BE6S   : 759mW, +200mW  , +576mW
A5EE008BB23BE5S   : 666mW, +216 mW, +592mW
A5EE008BB23BE4S   : 739mW   , +227mW, +604mW

sweet spot speed/static/cost appears to be -5

notes : Static power is  2x   Xilinx ZU2CG....
Turning on all those I/Os for the EMIF LPDDR4   hurts alot for Agilex5. ALthough the defaults for EMIF write/read and toggle rates  are high (50%) so, might be pessimistic.
But, the DSPs consume about half what XIlinx Ultrascale+ does....

FWIW Xilinx Ultrascale+ DSP consumption is 560mW (25x18)  for same task. So Agilex wins there .
(but Ultrascale+ can operate much faster -1 xilinx (slowest) = -2V Agilex (fast))  . 

Agilex 5 static and I/O power is massively higher, but when it gets busy, Agilex 5 fabric functions are lower power cost than Ultrascale+. Agilex5 may not be the best choice for battery operated devices... Agilex 5 is best when it is busy and heavily utilized, only then it has power advantages over Ultrascale+

Glen