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Altera_Forum's avatar
Altera_Forum
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15 years ago

delay in verilog

How can I insert one delay in a program but not in a simulation in verilog!?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

Thanks for your hint.

Anyway, I've tried but sop and eop signals seems to work fine.

The valid signal, I don't know. I'll take a picture of the image on the monitor becouse is quite difficult to explain the effect I am seeing..

Now I'll try to delay ONLY active data/sop/eop signals ( according to the valid signal) ant to (re)generate a valid signal as output locked to the data/sop/eop.