Altera_Forum
Honored Contributor
Honored Contributordelay in verilog
How can I insert one delay in a program but not in a simulation in verilog!?
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Altera_ForumHonored Contributor
Honored ContributorBefore we have to guess further about PLL usage, you should tell about the original problem as clear as possible.
Consider learning FPGA design step by step. You don't need to take all at once.
