delay in verilog

thanks for your reply.

Well, I am trying to make a video elaboration system with to branches. One branch should perform a lowpass effect on the video (a 2d fir, or a 2d median qith custom logic, not altera's ones) and the other branch should propagate video packets without elaborations. The custom block has a latency of (~)12 clock cycles, and I need the two branches to be aligned.

So, I was thinking to add a delay on the branch without elaboration, but it seems I am somhow wrong.

I did other kind of delay bloks for my system without using fsm, but they do not work too good..