delay in verilog

ok, this is my code. Right now, it SEEMS to work. If anyone would take a look and send me feedback, I would appreciate a lot.

--- Quote Start ---

module delay_finite_state (

clock,

reset,

ready,

dout_ready,

din_data,din_valid,din_sop,din_eop,

dout_data,dout_valid,dout_sop,dout_eop

);

input clock;

input reset;

input ready;

input [15:0]din_data;

input din_valid,din_sop,din_eop;

output reg [15:0] dout_data;

output reg dout_valid,dout_sop,dout_eop;

output dout_ready;

reg [1:0] fstate;

reg [1:0] reg_fstate;

reg [19:0] reg1,reg2,reg3,reg4,reg5,reg6,reg7,reg8,reg9,reg10,

reg11,reg12,reg13,reg14,reg15;

parameter idle=0,run=1;

always @(posedge clock)

begin

fstate <= reg_fstate;

end

always @(fstate or reset or ready)

begin

if (reset) begin

reg_fstate <= idle;

end

else begin

case (fstate)

idle: begin

if (ready) reg_fstate <= run;

// Inserting 'else' block to prevent latch inference

else

reg_fstate <= idle;

end

run: begin

reg1<={din_data, din_valid, din_sop, din_eop};

reg2<=reg1;

reg3<=reg2;

reg4<=reg3;

reg5<=reg4;

reg6<=reg5;

reg7<=reg6;

reg8<=reg7;

reg9<=reg8;

reg10<=reg9;

reg11<=reg10;

reg12<=reg11;

reg13<=reg12;

reg14<=reg13;

reg15<=reg14;

{dout_data,dout_valid,dout_sop,dout_eop}<=reg15;

if (~(ready)) reg_fstate <= idle;

// Inserting 'else' block to prevent latch inference

else reg_fstate <= run;

end

default: begin

$display ("Reach undefined state");

end

endcase

end

end

assign dout_ready=ready;

endmodule // SM1

--- Quote End ---