Altera_Forum
Honored Contributor
Honored Contributordelay in verilog
How can I insert one delay in a program but not in a simulation in verilog!?
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Altera_ForumHonored Contributor
Honored Contributoryou want to insert one "clock" delay?(I don't think so)
or delay for some nsec(or psec)? you can not create delay in HDL unless you put delayed clock with main clock. don't you have extra PLL out pins?
