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Altera_Forum's avatar
Altera_Forum
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14 years ago

Binary to Binary coded deicmal help

Hi guys,

I'm having trouble implementing a double dabble algorithm in verilog. These modules are supposed to produce 8bit BCD output from 5bit binary input.

However, it seems like the binary goes through unchanged! Which I assume means +3 never happens... But why? Any ideas?

Thanks in advance, the code I've got so far is below. 

module bcd(binary, bcd);
    input binary;
    output bcd;
    
    wire w0,w1,w2,w3;
    assign w0 = binary;
    add3 (.in(w0<<3), .out(w1));
    add3 (.in(w1<<1), .out(w2));
    add3 (.in(w2<<1), .out(w3));
    assign bcd = w3;
endmodule


module add3( in, out);
    input in;
    output out;
    reg out;
    
    always@(in)
    begin
        out = in;
        if(in>4) out = out + 3;
        if(in>4) out = out + 3;
    end
endmodule

14 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Just a wild gues. Your design is without clock (asynchronous) and could be running into logic hazards.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    Just a wild gues. Your design is without clock (asynchronous) and could be running into logic hazards.

    --- Quote End ---

    I tried adding a clock to the sensitivity list in "add3". That didn't help, or did I do it wrong?
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    if you just insert clock only in add3:

    always @ (posedge clock)

    ...

    than that should register the signal assignments and should be ok to make your design synchronous. The clock must be available as input if you are testing actual hardware.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Don't know where you get the algorithm, but it seems not to do what it should. Check with pencil and paper! Perhaps you can give a numerical example of what you want to achieve.

    There should be no principle problem to implement the algorithm completely asynchronously.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks for the speedy replies!

    --- Quote Start ---

    if you just insert clock only in add3:

    always @ (posedge clock)

    --- Quote End ---

    I tried using CLOCK_50 which I think should work on my DE1? And the display just read 0

    --- Quote Start ---

    Check with pencil and paper! Perhaps you can give a numerical example of what you want to achieve.

    --- Quote End ---

    Thats what is driving me absolutely crazy. I have done it hundreds of times on pen and paper and it's work.

    I'm trying to convert binary like 01011 to 0001 0001.

    Here's a run through.

    TENS|ONES|01011

    0000|0010|11 SHIFT 3 (no +3)

    0000|0101|1 SHIFT 4 (ones is >4 so +3)

    0000|1000|1

    0001|0001| SHIFT 5

    And the 5th shift gives you the BCD!
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    There should be no principle problem to implement the algorithm completely asynchronously.

    --- Quote End ---

    Certainly clock is not needed "in principle" just for this piece of work and especially for a beginner using finger buttons to generate inputs. But for a safer design methodology within a project and working on faster inputs I will use the clock.

    moreover, the statement:

    out = out + 3 implies feedback and I believe it can't survive asynchronously
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    I am a bit unsure about the feedback statements out = out + 3 ...etc.

    why not try: out = in + 3 if it is equivalent
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Thanks I tried that earlier and have just double checked. The result is the same.

  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    You better simulate the design functionally (away from timing issues) in modelsim or quartus and see all internal signals before you go to hardware.

    Even if you clock the out registers, the feedback will keep adding 3 if condition is true.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    You better simulate the design functionally (away from timing issues) in modelsim or quartus and see all internal signals before you go to hardware.

    Even if you clock the out registers, the feedback will keep adding 3 if condition is true.

    --- Quote End ---

    But each time it adds +3 it would have just reset out to in? Because of the block assignments? I'm fairly sure that's not happening for some reason. I tried removing the condition and +3 is happening. So either the condition is never true? Which I can't make sense of or the if clause is messing up the timming?

    I tried using modelsim but it's complaining about my not having a license :/