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Altera_Forum
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14 years ago

Binary to Binary coded deicmal help

Hi guys,

I'm having trouble implementing a double dabble algorithm in verilog. These modules are supposed to produce 8bit BCD output from 5bit binary input.

However, it seems like the binary goes through unchanged! Which I assume means +3 never happens... But why? Any ideas?

Thanks in advance, the code I've got so far is below. 

module bcd(binary, bcd);
    input binary;
    output bcd;
    
    wire w0,w1,w2,w3;
    assign w0 = binary;
    add3 (.in(w0<<3), .out(w1));
    add3 (.in(w1<<1), .out(w2));
    add3 (.in(w2<<1), .out(w3));
    assign bcd = w3;
endmodule


module add3( in, out);
    input in;
    output out;
    reg out;
    
    always@(in)
    begin
        out = in;
        if(in>4) out = out + 3;
        if(in>4) out = out + 3;
    end
endmodule

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  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    out = out + 3 implies feedback

    --- Quote End ---

    No it doesn't. It's a simple sequential expression.

    --- Quote Start ---

    I have done it hundreds of times on pen and paper and it's work.

    --- Quote End ---

    I checked one example (dec 22 / hex 16, should give hex 22), and it was wrong.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    --- Quote Start ---

    I checked one example (dec 22 / hex 16, should give hex 22), and it was wrong.

    --- Quote End ---

    TENS|ONES|22

    0000|0000|10110

    0000|0101|10 (third shift) ones>4 so +3

    0000|1000|10 (fourth shift)

    0001|0001| (shift 5)

    0010|0010|

    It works. I didn't invent double dabble.
  • Altera_Forum's avatar
    Altera_Forum
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    14 years ago

    Just noticed you are adding 3 to ones yet the code adds 3 to all in bits.

    Shouldn't you say:

    if in(8:5) > 4 out(8:5) = out(8:5)+3; as the tens
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    14 years ago

    --- Quote Start ---

    Just noticed you are adding 3 to ones yet the code adds 3 to all in bits.

    Shouldn't you say:

    if in(8:5) > 4 out(8:5) = out(8:5)+3; as the tens

    --- Quote End ---

    Oh my, I can;t believe I didn't spot that in two days! It's working much better now. Still not working great but I can work on that in the morning. Thanks so much!

    Update:

    I removed the final add3 now it works perfectly.

    Here's the final code in working order. 

    module bcd(in, out);
    input in;
    output out;
    
    wire w0,w1,w2,w3;
    assign w0 = in;
    add3 (.in(w0<<3), .out(w1));
    add3 (.in(w1<<1), .out(w2));
    assign w3 = w2 << 1;
    assign out = w3;
endmodule

    module add3(in, out);
    input in;
    output out;
    reg out;
    
    always@(*)
    begin
        out = in;
        if(in>4) out = in + 3;
        if(in>4) out = in + 3;
    end
endmodule