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Altera_Forum
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14 years ago

Binary to Binary coded deicmal help

Hi guys, I'm having trouble implementing a double dabble algorithm in verilog. These modules are supposed to produce 8bit BCD output from 5bit binary input. However, it seems like the binary ...
Altera_Forum's avatar
Altera_Forum
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14 years ago

You better simulate the design functionally (away from timing issues) in modelsim or quartus and see all internal signals before you go to hardware.

Even if you clock the out registers, the feedback will keep adding 3 if condition is true.