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Altera_Forum's avatar
Altera_Forum
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14 years ago

Binary to Binary coded deicmal help

Hi guys, I'm having trouble implementing a double dabble algorithm in verilog. These modules are supposed to produce 8bit BCD output from 5bit binary input. However, it seems like the binary ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

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Just a wild gues. Your design is without clock (asynchronous) and could be running into logic hazards.

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I tried adding a clock to the sensitivity list in "add3". That didn't help, or did I do it wrong?