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Altera_Forum's avatar
Altera_Forum
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14 years ago

Binary to Binary coded deicmal help

Hi guys, I'm having trouble implementing a double dabble algorithm in verilog. These modules are supposed to produce 8bit BCD output from 5bit binary input. However, it seems like the binary ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

if you just insert clock only in add3:

always @ (posedge clock)

...

than that should register the signal assignments and should be ok to make your design synchronous. The clock must be available as input if you are testing actual hardware.