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You better simulate the design functionally (away from timing issues) in modelsim or quartus and see all internal signals before you go to hardware.
Even if you clock the out registers, the feedback will keep adding 3 if condition is true.
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But each time it adds +3 it would have just reset out to in? Because of the block assignments? I'm fairly sure that's not happening for some reason. I tried removing the condition and +3 is happening. So either the condition is never true? Which I can't make sense of or the if clause is messing up the timming?
I tried using modelsim but it's complaining about my not having a license :/
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