AltsynRAM : 1 clock cycle Read/Write performance

Note that Stratix III/IV have a logic -> memory similar to the CLB. In general it is still treated as synchronous, but I think it can do asynchronous reads to(i.e. test it out before going down that road). I've converted a number of Xilinx designs where the user complained about not having asynchronous reads, only to find they had a register right next to it that could be absorbed, but it sounds like your architecture really depends on it. I also wonder if you could do some sort of "trick", like maybe having two copies of the RAM, where you ping-pong back and forth(I don't fully get what you're doing, so that may not make any sense).

Ok Rysc.

I have always heard clock cycles referred to as the number of clocks in your datapath. (That way it always adds up, i.e. two components put together with clock cycles of 2 would have a total clock cycle delay of 4, but in your methodology it would only be 3, which is counterintuitive. That's why I was confused.) But yes, if the critical path in your design is solely dependent on an asynchronous read from memory, then Cyclone II's embedded memory is not good for your application.

Semantics apart (I never talked about "cycle of latency", I talked about number of clock cycles=performance), my application is for a soft microprocessor, and the performance with Altera RAM I use (Cyclone II) is half of the obtained with Xilinx RAM.

I guess it's semantics, but if you drew the memory access as a schematic, there is only one register along the path, so that is generally referred to as one clock cycle of latency. You're basically saying you need the access in less than one clock cycle so it's completely out by the next clock cycle, or an asynchronous read. What device and what speed is the clock? If the clock is slow enough, then you could read on the falling edge of the clock, so it's available a half cycle earlier.

Rysc, then with ALTERA RAM I need 2 clock cycles for a read.

Something seems off. There are no asynchronous RAMs(MLABs are, but they're treates synchronously), but there is also nothing that requires two registers. You register the address, and the data comes out combinatorially later. There is no need for a second clock.

I guess the available options on the RAM block depends on the FPGA family, and you may not be able to remove the input registers on some families.

I disable output port registers, but address input port is registered. So, I need 2 clocks in a read cycle. In the first clock, the addres is registered and the data appears on the second clock.

You must disable output ports registers