AltsynRAM : 1 clock cycle Read/Write performance

I have always heard clock cycles referred to as the number of clocks in your datapath. (That way it always adds up, i.e. two components put together with clock cycles of 2 would have a total clock cycle delay of 4, but in your methodology it would only be 3, which is counterintuitive. That's why I was confused.) But yes, if the critical path in your design is solely dependent on an asynchronous read from memory, then Cyclone II's embedded memory is not good for your application.