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Honored Contributor
Honored ContributorAltsynRAM : 1 clock cycle Read/Write performance
Hi all, I need a 128 bytes RAM block, internal to FPGA (cycloneII). I would like achieve 1 clock read and 1 clock write performance. In Xilinx this is done with sync write and async read RAM. I...
Altera_ForumHonored Contributor
Honored ContributorI have always heard clock cycles referred to as the number of clocks in your datapath. (That way it always adds up, i.e. two components put together with clock cycles of 2 would have a total clock cycle delay of 4, but in your methodology it would only be 3, which is counterintuitive. That's why I was confused.) But yes, if the critical path in your design is solely dependent on an asynchronous read from memory, then Cyclone II's embedded memory is not good for your application.
