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Altera_Forum
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16 years ago

AltsynRAM : 1 clock cycle Read/Write performance

Hi all, I need a 128 bytes RAM block, internal to FPGA (cycloneII). I would like achieve 1 clock read and 1 clock write performance. In Xilinx this is done with sync write and async read RAM. I...
Altera_Forum's avatar
Altera_Forum
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16 years ago

Semantics apart (I never talked about "cycle of latency", I talked about number of clock cycles=performance), my application is for a soft microprocessor, and the performance with Altera RAM I use (Cyclone II) is half of the obtained with Xilinx RAM.