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Altera_Forum
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17 years ago

AltsynRAM : 1 clock cycle Read/Write performance

Hi all, I need a 128 bytes RAM block, internal to FPGA (cycloneII). I would like achieve 1 clock read and 1 clock write performance. In Xilinx this is done with sync write and async read RAM. I...
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Altera_Forum
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17 years ago

Note that Stratix III/IV have a logic -> memory similar to the CLB. In general it is still treated as synchronous, but I think it can do asynchronous reads to(i.e. test it out before going down that road). I've converted a number of Xilinx designs where the user complained about not having asynchronous reads, only to find they had a register right next to it that could be absorbed, but it sounds like your architecture really depends on it. I also wonder if you could do some sort of "trick", like maybe having two copies of the RAM, where you ping-pong back and forth(I don't fully get what you're doing, so that may not make any sense).