Understanding the Purpose of Active Discharge Circuits in FPGA Power Design (Terasic DE10 Reference)

Hello everyone,

While reviewing the schematics for a Terasic DE10 board, I noticed a specific circuit block on the power rails.

See attached image

From my understanding of the schematic, when a specific Enable (EN) signal drops or is disabled, this circuit actively shorts the power rails to ground.

My question is regarding the fundamental design here:

If the power to the board drops, or the EN signal to the voltage regulators is pulled low, the voltage to the FPGA will naturally stop being supplied anyway. Why is there a need to spend BOM cost and board space on actively shorting the rails to ground? I would love a more in-depth explanation from a board-level design perspective.

What exact failure modes or risks does this active discharge circuit prevent in FPGAs?

Is this considered a mandatory best practice for all Agilex/Stratix/Cyclone designs, or is it only necessary under specific power supply topologies?

Thank you for the insights!