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New ContributorUnderstanding the Purpose of Active Discharge Circuits in FPGA Power Design (Terasic DE10 Reference)
Hello everyone,
While reviewing the schematics for a Terasic DE10 board, I noticed a specific circuit block on the power rails.
See attached image
From my understanding of the schematic, when a specific Enable (EN) signal drops or is disabled, this circuit actively shorts the power rails to ground.
My question is regarding the fundamental design here:
If the power to the board drops, or the EN signal to the voltage regulators is pulled low, the voltage to the FPGA will naturally stop being supplied anyway. Why is there a need to spend BOM cost and board space on actively shorting the rails to ground? I would love a more in-depth explanation from a board-level design perspective.
What exact failure modes or risks does this active discharge circuit prevent in FPGAs?
Is this considered a mandatory best practice for all Agilex/Stratix/Cyclone designs, or is it only necessary under specific power supply topologies?
Thank you for the insights!
3 Replies
FakhrulA_alteraRegular Contributor
Hi sovad,
From the schematic, this looks like a power-down fast discharge circuit. When the power enable signal is turned off, the MOSFETs are enabled and the related FPGA power rails are discharged to GND through low-value resistors.
The purpose is to remove remaining voltage on the rails faster after power-off. This can help avoid leftover voltage, slow power-down, quick power-cycle issues, or possible back-powering through other devices.
This is mainly a board-level power design choice and is not a general mandatory requirement for all Altera FPGA designs. It depends on the power design, regulator behavior, rail capacitance, and sequencing needs.
For the exact reason this was added on the Terasic DE10 board, please check with Terasic, as this is part of their board implementation.
FvMSuper Contributor
Cyclone 10 GX, Arria 10 and Agilex have specific requirements for power rail sequencing, partly including power-down sequence specifications. Active discharge can be required to fulfill it. I feel that respective device handbooks give detailed reasoning which parameters should be implemented.
Can you tell which DE10 board schematic are you quoting?
Regards Frank
- FakhrulA_altera
Hi sovad,
Just checking if there is any update from your side.
As Frank mentioned, some FPGA families such as Cyclone 10 GX, Arria 10, and Agilex may have specific power sequencing or power-down requirements. In some designs, an active discharge circuit can help meet these requirements by discharging the power rails faster.
For the Terasic DE10 board, the exact reason depends on the specific schematic and Terasic’s board-level design. Please check with Terasic if you need confirmation on their implementation.
Since there has been no further response, we will consider this thread closed. If you have any further questions, please feel free to post a new update.
