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Honored Contributor
Honored ContributorAltsynRAM : 1 clock cycle Read/Write performance
Hi all, I need a 128 bytes RAM block, internal to FPGA (cycloneII). I would like achieve 1 clock read and 1 clock write performance. In Xilinx this is done with sync write and async read RAM. I...
Altera_ForumHonored Contributor
Honored ContributorRysc, then with ALTERA RAM I need 2 clock cycles for a read.
In the 1st clock the address is registrered and afterthat (during the 2nd clock) the data comes out (combinatorially or not :)). I'm wrong?. It's possible read a data from a ALTERA RAM in ONLY 1 clock?.
